Clock skew problems can manifest themselves in several environments, including but not limited to, chip-level, System-on-Chip (SoC), and board/system level. As an example of chip-level skew, consider a microprocessor whose synchronous circuitry (i.e. flip-flops) is spread across a wide area of an integrated circuit chip. Now consider a single clock signal that is to be distributed across the chip in such a way that the rising edge of each clock cycle reaches each flip-flop at the same point in time. Skew in this environment is becoming a more problematic issue as device sizes shrink, clock speeds increase, and chip size increase. This means that the path delay in a signal trace may differ by many cycles of a clock period from one section of the chip to another. With system clock frequencies well into the gigahertz range, clock skews on the order of picoseconds can produce adverse affects on system performance, or even disrupt system functionality.
A similar problem arises in so-called “System-on-Chip” scenarios. A clock signal should be routed to a baseband section, a microprocessor, and a memory block (or other functional blocks) with minimal skew. Again, the length of an on-chip signal path from the clock generator to the various functional blocks can be long enough to introduce significant delay and thereby affect the maximum operating frequency. Skew can also be a problem on a board level system for the same reasons outlined above. But on a board level system, the problem can be even further exacerbated by even longer signal traces and more severe loading caused by signal paths that are routed on and off chips and other components.